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QPHY-DDR3 Software Option

917717 Rev C 39

Measure timing from DQS at VREF to DQ rising at VIH(ac)min and falling at VIL(ac)max.

Figure 17 - Data output (read) timing [JESD79-3D figure 27]

tQH, DQ/DQS Output Hold Time From DQS

This measures the timing from DQS at VREF to DQ at VIH(dc) (rising edge) or VIL(dc) (falling edge). See

figure 22.

tDQSCK, DQS Output Access Time from CK/CK #

Time from CK rising at VREF level to DQS rising at VREF level.

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Teledyne-lecroy QPHY-DDR3 Manual do Utilizador Página 39